View SCN0080GA_1735128.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

data sheet (v3) 2005 oct 05 scn0080g_a, scn0080g_b 80-segment dot-matrix stn lcd driver to improve design and/or performance, avant electronics may make changes to its products. please contac t avant electronics for the latest versions of its products d a t a sh eet
2005 oct 05 2 of 22 data sheet (v3) 80-segment dot-matr ix stn lcd driver scn0080g_a, scn0080g_b avant electronics 1general 1.1 description the scn0080g_a and the scn0080g_b are two 80-segment dot -matrix stn lcd drivers. they are designed to be paired with the scn6400g 64-common driver. the only di fference between the scn0080g_a and the scn0080g_b is their pin assignment. the pin assignment of the scn0080g_b is a mirrored version of the scn0080g_a. two types of pin assignments make pcb layout more flexible and increase component density. 1.2 features ? ? ? ? ? ? ? ? ? ? ?
2005 oct 05 3 of 22 data sheet (v3) 80-segment dot-matr ix stn lcd driver scn0080g_a, scn0080g_b avant electronics 2 functional block diagram and description 2.1 functional block diagram fig.1 functional block diagram v1 v3 v4 v ee dispoff sdi/di4 di3 di2 di1 p/s cdi cp load cdo m vss vdd 2nd latch (80 bits) parallel/serial address decoder address counter chip disable & latch control data bus interface (5 bits) o1 o2 o3 o79 o80 80 4-level lcd driver circuit (80 bits) hv logic and level shifter (80 bits) 1st latch (80 bits) serial/parallel 80 80 4 20 5 address decoder control high voltage area
2005 oct 05 4 of 22 data sheet (v3) 80-segment dot-matr ix stn lcd driver scn0080g_a, scn0080g_b avant electronics 3 pinning information 3.1 pinning diagram fig.2 pin diagram of lqfp/qfp100 package 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 32 33 31 o2 o3 o5 o7 o9 o10 o12 o13 o15 o18 o19 o20 o21 o22 o4 o6 o8 o11 o14 o17 o16 o23 o24 o25 o26 o27 o28 o29 o30 o1 o79 o78 o76 o74 o72 o71 o69 o68 o66 o63 o62 o61 o60 o59 o77 o75 o73 o70 o67 o64 o65 o58 o57 o56 o55 o54 o53 o52 o51 o80 o50 o49 o48 o47 o46 o45 o44 o43 o42 o41 o40 o39 o38 o37 o36 o35 o34 o33 o32 o31 nc cdo p/s nc v3 nc v dd v4 v ss dispoff v ee v1 m di1 di2 di3 load cdi cp sdi/di4 scn0080g_a 123456789101112131415161718192021222324252627282930 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 32 33 31 o79 o78 o76 o74 o72 o71 o69 o68 o66 o63 o62 o61 o60 o59 o77 o75 o73 o70 o67 o64 o65 o58 o57 o56 o55 o54 o53 o52 o51 o80 o2 o3 o5 o7 o9 o10 o12 o13 o15 o18 o19 o20 o21 o22 o4 o6 o8 o11 o14 o17 o16 o23 o24 o25 o26 o27 o28 o29 o30 o1 o31 o32 o33 o34 o35 o36 o37 o38 o39 o40 o41 o42 o43 o44 o45 o46 o47 o48 o49 o50 cp cdi di3 load v1 v dd nc m di2 sdi/di4 di1 v3 v4 v ee v ss p/s nc cdo nc dispoff scn0080g_b 123456789101112131415161718192021222324252627282930 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 fig.3 pin diagram of lqfp100/qfp100 package
2005 oct 05 5 of 22 data sheet (v3) 80-segment dot-matr ix stn lcd driver scn0080g_a, scn0080g_b avant electronics 3.2 signal description table 2 pin signal description. to avoid a latch-up effect at power-on: v ss 0.5 v < voltage at any pin at any time < v dd + 0.5 v . pin number symbol i/o description scn0080g_ a scn0080g_ b 1~80 80~1 o1~o80 output segment driver output. please refer to table 3 for output voltage level. 99 82 cdi input chip disable pin. when cdi=high, on-chip data reception circuit is disabled and data can not be sent into the scn0080g_a, scn0080g_b. when cdi=low, data can be sent into the scn0080g_a, scn0080g_b. 92, 89, 88 89, 92, 93 v1, v3, v4 input lcd bias voltage. v1 and v ee are selected levels. v3 and v4 are unselected levels. 87 94 v ee input negative power supply for lcd bias. 93 88 m input frame signal, for generating alternating lcd bias voltages. 98 83 load input display data (80 bits) latch clock. at the falling edge of the load signal, 80-bit segment data is trans ferred from the first latch to the second latch for output. ( refer to fig. 1 , functional block diagram. 86 95 v ss input ground. 84 97 dispoff input display disable. when dispoff =l, the outputs o1~o81 are all at a fixed level of v1. 91 90 v dd input power supply for control logic. 85 96 p/s input selection of parallel or serial interface with a controller. when p/s= high, 4-bit parallel interface is selected. when p/s=low, serial interface is selected. 81, 83, 90 91, 98, 100 nc no connection. these pins are not used in application and must be left open.
2005 oct 05 6 of 22 data sheet (v3) 80-segment dot-matr ix stn lcd driver scn0080g_a, scn0080g_b avant electronics 97, 96, 95, 94 84, 85, 86, 87 sdi/di4 ~ di1 input 4-bit parallel data input or 1-bit serial input. when 4-bit parallel data bus interferes is selected, the 4 bits of data are latched into the scn0080g_a, scn0080g_b at the falling edge of the cp clock. please refer to fig 4 . when 1-bit serial interface is selected, data is input to the sdi/di4 pin. in this interface mode, di1~di3 should be tied either to high or to low. 100 81 cp input display data latch clock. 4 bits of display data (di1~di4) are latched into the internal 80-bit latch at the falling edge of cp. please refer to fig 4. 82 99 cdo output cascading output when the scn0080g_a, scn0080g_b are used in cascade. pin number symbol i/o description scn0080g_ a scn0080g_ b
2005 oct 05 7 of 22 data sheet (v3) 80-segment dot-matr ix stn lcd driver scn0080g_a, scn0080g_b avant electronics 4 functional description 4.1 segment output drive (o1~o80) the voltage level of the outputs o1~o80 is determined by input data (display data), m (frame signal), and dispoff , as given in the following table. table 3 output voltage level of o1~o80 m data dispoff output l l h v3 l h h v1 h l h v4 h h h v ee x x l v1 in the above table, x= don?t care and must be tied either to h or l. 4.2 display data inputs (di1~di4) the scn0080g_a, scn0080g_b has a 4-bit parallel data bus (di1 ~di4) to interface with a controller. a logic high of a bit represents an on cell (b lack pixel on the lcd screen). table 4 data bits display data lcd drive output lcd display h selected level (v1, v ee ) on l unselected level (v3, v4) off 4.3 sequence of data input when 4-bit parallel interface is selected. when 4-bit parallel interface mode is selected , the 4-bit data that is first latched goes to o77 ~ o80 and the 4-bit data that is last latched goes to o1 ~ o4. fig.4 sequence/direction of display data input di1 di2 di3 di4 di1 di2 di3 di4 di1 di2 di3 di4 o1 o2 o3 o4 o5 o6 o7 o8 o77 o78 o79 o80 di1 di2 di3 di4 first latched last latched 4 bits
2005 oct 05 8 of 22 data sheet (v3) 80-segment dot-matr ix stn lcd driver scn0080g_a, scn0080g_b avant electronics 5 absolute maximum rating table 5 absolute maximum rating v dd = 5 v ? 0 ? >
2005 oct 05 9 of 22 data sheet (v3) 80-segment dot-matr ix stn lcd driver scn0080g_a, scn0080g_b avant electronics 6 dc characteristics table 6 dc characteristics v dd = 5 v 252 0.0 ? 0.4 ? >
2005 oct 05 10 of 22 data sheet (v3) 80-segment dot-matr ix stn lcd driver scn0080g_a, scn0080g_b avant electronics 7 ac characteristics fig.5 ac characteristics 0.2v dd t setup t hold t d cp 0.8v dd 0.2v dd 0.8v dd 0.2v dd 0.8v dd 0.2v dd 0.8v dd 0.2v dd t cl t lc 0.8v dd 0.2v dd t wc load t rl t wl t fl 0.2v dd t r t f 0.2v dd cp di1~di3 cdo t wc sdi table 7 ac characteristics v dd = 5 v 25 80
2005 oct 05 11 of 22 data sheet (v3) 80-segment dot-matr ix stn lcd driver scn0080g_a, scn0080g_b avant electronics 8 output timing diagram fig.6 output timing diagram 1 2 3 19 20 21 ic number 1 data acquisition period ic number 2 data acquisition period ic number 3 data acquisition period ic number n data acquisition period cp di1 di4 load o1~o80 cdo(no.n) cdo(no.3) cdo(no.2) cdo(no.1) one scan line ( n x 80 pixels )
2005 oct 05 12 of 22 data sheet (v3) 80-segment dot-matr ix stn lcd driver scn0080g_a, scn0080g_b avant electronics 9 timing chart ( 1/240 duty, 1/16 bias) 9.1 1/240 duty timing chart 2 fig.7 1/240 duty timing chart load 01~o80 m load di1~di4 cp d1~d80 m 12 240 1 2 240 1 240 9.2 1/16 bias fig.8 1/16 bias load 240 1 2 240 1 2 240 1 2 latch data m vdd (v1) va vb (v3) l h l l h l l h l o1 ~o80 vc (v4) vd ve (v ee ) va = v dd - (1/16) v lcd vb = v dd - (2/16) v lcd v lcd vc = v dd - (14/16) v lcd vd = v dd - (15/16) v lcd ve = v dd - (16/16) v lcd v lcd vdd v dd v1 v3 v4 vee r r 12r r r va vb vc vd ve vr v ss v ee refer to fig. 9 for enlarged view.
2005 oct 05 13 of 22 data sheet (v3) 80-segment dot-matr ix stn lcd driver scn0080g_a, scn0080g_b avant electronics 9.3 bias circuit v lcd v dd v dd v1 v3 v4 v ee r r 7r r r va vb vc vd ve vr v ss fig.9 lcd bias voltage v ee scn0080g_a va = v dd - (1/11) v lcd vb = v dd - (2/11) v lcd vc = v dd - (9/11) v lcd vd = v dd - (10/11) v lcd ve = v dd - (11/11) v lcd bias for the scn0080g_b is the same as that for the scn0080g_a.
2005 oct 05 14 of 22 data sheet (v3) 80-segment dot-matrix stn lcd driver scn0080g_a, avant electronics 10 200 x 640 application scn0080g_b m scn0080g_b m 200 x 640 lcd panel cdi load sdi cp load cp m m 2 load sdi cp load sdi cp m m cdo cdi m m sdi cp load m m dio1 dio1 scn6400g scn6400g cp cp 4 4 v1,v2 v5,v ee 6 4 do1 eo1 flm sap1024b, lc7980 m cl1 cl2 od2 ed2 v1 v dd r r r r v2 v3 v4 v5 7r m m m m 4 scn0080g_a scn0080g_a scn0080g_a scn0080g_a dio64 1 2 159 160 161 162 319 320 321 322 479 480 481 482 639 640 1280 1279 1122 1121 1120 1119 962 961 960 959 802 801 800 799 642 641 controller (scan data) (frame signal) v1, v2 v5, v ee o1~o64 o1~o64 o1~o36 o1~o36 com1~com100 com101~com200 scn0080g_b v1, v3, v4, v ee m scn0080g_b m v1, v3, v4, v ee v ee ( -11 ~~ -13 volts) scn0080g_a scn0080g_b scn0080g_a scn0080g_b cdo cdo cdi cdi m m cdo cdi scn0080g_a scn0080g_a scn0080g_b scn0080g_b od1, ed1 od2, ed2 cp load 2
2005 oct 05 15 of 22 data sheet (v3) 80-segment dot-matr ix stn lcd driver scn0080g_a, scn0080g_b avant electronics 11 100 x 240-pixel application the following diagram illustrates an example of usi ng three scn0080g_a (or scn0080g_b) and two scn6400g to design a 100 x 240-dots lcd panel. the duty cycle of the desi gn is 1/100. for cascading appl ication, cascading output (cdo) of the previous chip should be connected to the cascading input of the next chip. m o35 ~ p/s di1 di2 di3 soi cp m p/s di1 di2 di3 soi cp m load load segment line (n) common line (m) (m, n): pixel address scan data scn6400g scn6400g scn0080g_a (scn0080g_b) scn0080g_a (scn0080g_b) scn0080g_a (scn0080g_b) 100 x 200-pixel lcd panel dio1 rs/ls o1 o2 cp m o63 o64 dio64 o1 o2 dio1 cp rs/ls dio64 p/s di1 di2 di3 soi cp m load data shift clock serial data alternating signal data latch clock o1 o2 o79 o80 o1 o2 o80 o1 o80 cdi cdo cdi cdo cdi cdo 63, 1 63, 2 64, 1 64, 2 65, 1 65, 2 66, 1 66, 2 64, 80 64, 81 64, 79 63, 79 63, 80 63, 81 63, 82 64, 82 65, 79 65, 80 65, 81, 65, 82 66, 79 66, 80 66, 81 66, 82 100, 1 100, 2 100, 79 100, 80 100, 81 100, 82 1, 1 1, 2 2, 1 2, 2 1, 79 1, 80 1, 81 1, 82 1, 160 1, 161 1, 240 2, 240 63, 160 63, 161 63, 240 64, 160 64, 161 64, 240 65, 160 65, 161 65, 240 100, 160 100, 161, 100, 240 66, 160 66, 161 66, 240 1, 79 o37~o64 are not used and should be left open fig.10 100 x 240-pixel application
2005 oct 05 16 of 22 data sheet (v3) 80-segment dot-matr ix stn lcd driver scn0080g_a, scn0080g_b avant electronics 12 timing diagram for 100 x 240-pixel application m load cp sdi cp ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ o1 o2 o80 o1 o80 o1 o80 load #1 dio1 m sdi load m 1, 1 1, 2 1, 79 1, 80 1, 81 1, 160 1, 161 1, 240 cdo (chip #2) cdo (chip #1) cdo (chip #3) chip #1 data read chip #2 data read chip #3 data read 1st scan line(240 pixels) 2nd scan line 100th scan line 1,1 1,2 1,239 1,240 2,1 2,240 100,240 100,1 fig.11 timing diagram for 100 x 240-pixel application chip #1 chip #2 chip #3 1,1 1,2 1,80 1,81 1,160 1,161 1,240 2,1 2,2 2,80 2,81 2,160 2,161 2,240 98,1 98,2 98,80 98,81 98,160 98,161 98,240 99,1 99,2 99,80 99,81 99,160 99,161 99,240 100,1 100,2 100,80 100,81 100,160 100,161 100,240 1,1 1,2 1,80 1,81 1,160 1,161 1,240 99,1 99,2 99,80 99,81 99,160 99,161 99,240 100,1 100,2 100,80 100,81 100,160 100,161 100,240 one frame ( 100 x 240 bits) scn0080g_a, scn0080g_b output data
2005 oct 05 17 stn lcd driver data sheet (v3) 80-segment dot-matrix stn lc d driver scn0080g_a, scn0080g_b 13 applications where segment data is not a multiple of 4 load ~ ~ 100 x 230-pixel lcd panel o1 o80 scn0080g chip #1 o1 o80 scn0080g chip #2 o1 o70 scn0080g chip #3 m,1 m,2 m,228 m,229 m,230 m+1,1 m+1,2 m+1,228 m+1,229 m+1,230 sdi if serial data is sent according to the above timing diagram, data pixels (m,229), (m,230), (m+1,1), and (m+1,2) will not be output to o69, o70 of chip #3, because the scn0080g_a (or the scn0080g_b) accepts both parallel and serial input data in a 4-bit unit. fig.12 application where segment number is not multiples of 4. ~ load sdi m,1 m,2 m,228 m,229 m,230 m,231 m,232 dummy data valid display data multiple of 4 a timing diagram for applications where segment number is not a multiple of 4 is given above. in this application, the pixel (m,231) and the pixel (m, 232) are, respectively, output on o71 and o72 of chip #3. but, because these two outputs are not physically connected to the panel, they are not valid outputs. fig.13 timing diagram for applications where segment number is not multiples of 4.
2005 oct 05 18 stn lcd driver data sheet (v3) 80-segment dot-matrix stn lc d driver scn0080g_a, scn0080g_b 14 pin circuits table 8 mos-level schematics of all input, output, and i/o pins. symbol input/ output circuit notes cdo output vdd vss vss vdd cp, load, di1~sdi/di4, p/s, m, cdi, dispoff inputs vss vdd vss vdd o1~o80, v1, v3, v4, v ee driver outputs, high voltage inputs on n= 1 ~ 80 v1 v3 v4 vee vdd en1 en2 en3 vdd vdd vee vee vee vdd v ee en4 vdd vee
2005 oct 05 19 stn lcd driver data sheet (v3) 80-segment dot-matrix stn lc d driver scn0080g_a, scn0080g_b 15 application notes 1. it is recommended that the following power-up sequence be followed to ensure reliable operation of your display system. as the ics are fabricated in cm os and there is intrinsic latch-up problem associated with any cmos devices, proper power-up sequence can reduce the danger of triggeri ng latch-up. when powering up the system, control logic power must be powered on first. when powering down the system, cont rol logic must be shut off later than or at the same time with the lcd bias (v ee ). vdd signal v ee 5v 0v -30v 0~50 ms 1 second (minimum) 0 second 0 second (minimum) (minimum) 0~50 ms 1 second (minimum) fig.14 recommended power up/down sequence
2005 oct 05 20 of 22 data sheet (v3) 80-segment dot-matrix stn lcd driver scn0080g_a, avant electronics 16 package information scn0080g_a qfp100 package outline drawing
2005 oct 05 21 stn lcd driver data sheet (v3) 80-segment dot-matrix stn lc d driver scn0080g_a, scn0080g_b 17 soldering 17.1 introduction there is no soldering method that is ideal for all ic package s. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circui ts with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. for more in-depth account of soldering ics, please refer to dedicated reference materials. 17.2 reflow soldering reflow soldering techniques ar e suitable for all qfp packages. the choice of heating method may be infl uenced by larger plastic qfp packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolute ly dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can c ause cracking of the plastic body . for more information, please contact avant for drypack information. reflow soldering requires solder paste (a suspension of fi ne solder particles, flux and bi nding agent) to be applied to the printed-circuit board by screen prin ting, stencilling or pressure-syri nge dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typica l reflow temperatures range from 215 to 250 q c. preheating is necessary to dry the paste and ev aporate the binding agent. preheating duration: 45 minutes at 45 q c. 17.3 wave soldering wave soldering is not recommended for qfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possib ility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: x a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. x the footprint must be at an angle of 45 q to the board direction and must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 q c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 q c within 6 seconds. typical dwell time is 4 seconds at 250 q c. a mildly-activated flux will elimi nate the need for removal of corrosiv e residues in most applications. 17.4 repairing soldered joints fix the component by first soldering two diagonally- oppos ite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 q c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 q c.
2005 oct 05 22 stn lcd driver data sheet (v3) 80-segment dot-matrix stn lc d driver scn0080g_a, scn0080g_b 18 life support applications avant products are not designed for use in life support appliances, devices, or systems where malfunction of these products may leads to personal injury. av ant customers using or selling these pr oducts for use in such applications do so at their own risk and agree to fully indemnify avant fo r any damages resulting from such improper use or sale.

▲Up To Search▲

Price & Availability of SCN0080GA

	To Download SCN0080GA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .